IC Testing

TRI sells Digital IC Testers (TR6010, TR6020, TR6836), Mixed-Signal IC Testers (TR6850, TR6850S, TR6800) and will soon have the high-end TR6600 which provides testing for Mixed-Signal ICs and RF ICs and is ideal for System-on-Chip (SOC) products.

TRI’s testers are ideal for test houses as well as design firms. All TRI IC testers have multi-site testing capability and can test both wafers and packaged chips.

TRI’s testers feature muti-site testing. This means that a TRI tester can test two, four or eight dies on a wafer simultaneously, not just a single chip. This greatly increases test throughput and helps reduce our customers’ overall testing costs.

There are many advantages to wafer testing, the first is that the earlier a defect is found, the cheaper it is to fix. Defects in finished goods can be very costly in terms of warranty and replacement costs. Also, probing wafers --
· Eliminates bad devices before packaging and final test

· Gives immediate yield information and analysis at the wafer level

· Provides true package-related failures

· Helps to monitor yield and quality for high-yield products

The tester applies a sequence of drive data to the device and simultaneously compares the outputs against expected results. Each drive/compare cycle is called a digital vector. Depending on the model, TRI testers support 4M (mega-), 8M or 16M vectors per test pin. The upcoming TR6600 supports up to 32M vectors.

The TR6850S features all the capabilities of the TR6850 in an economical, smaller footprint.

You can add a Multi-I/O card to expand the parallel printer port, then the tester can use the main printer port and the printer can use the other port on the I/O card.

Yes, the program can be used with the new software, but you should add "#define VER002A" in front of "#include " of the old version. If necessary, the claim of "eotest()" should be deleted.

Yes. The TR6010 has two commands, SEQBEG and SEQEND. In these two command blocks, the other commands in between will execute site by site.

Without Local Memory Board, the pattern cannot be input for functional test. DC test will be no problem.

If the pattern's depth input is smaller than the minimum depth of Local Memory board, it will be no problem; if the depth is between the minimum and the maximum, Local Memory board is suggested to be put from left to right, from deep to shallow, and the width and depth should match the pattern's need. The other shallow Local Memory boards do not need to input any pattern.

Each PEB16 Board has a PMU, so a PMU can be added by adding a PEB16 Board. Also, an HVPMU Board can be added which has two HVPMU. You can adjust the quantity of PEB16 or HVPMU Board to have the number of PMU you want.

Set the Waveform Format to “RTZ” and Stop time after TP ending.

When executing Multi-Site Test, the hardware distribution is for maximum sources. This means that when the quantity of PEB16 Boards is fixed, the quantity of each Site's PEB16 Board is different and the Site location is different too.

After the system software is updated, you have to compile and link the program again for a new test execution file.

There are 32 Software BINs and 8 Hardware BINs. Every four Software BINs correspond to a Hardware BIN. For example, Software BINs 1, 9, 17, and 25 correspond to Hardware BIN 1 output. Software BINs 2, 10, 18, and 26 correspond to Hardware BIN 2 output. BINs 1 to 8 sent by EPPinf Board JP1 to JP4 are Hardware BINs. Software BINs can be obtained from system software summary.

There are 0, 1, L, H, Z, X, J, and Q in TR6010 pattern symbol, and "Z" can test Tri-state output IC. In order to test if the IC output is High-Z, you have to write "Z" in pattern and add bias in the output pin. The voltage should be set between VOL and VOH, with the optimal setting = (VOL+VOH)/2. Thus, when the output pin voltage is between VOL and VOH, it is "Pass", otherwise it is "Fail".