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TR6836 is a 33MHz logic IC tester with the best price-performance ratio in the market. It is capable of conducting functional pattern testing and DC parametric testing. Featuring a user-friendly test program development environment, rich debugging & analytic tools, compact size, and a highly-integrated design makes the TR6836 a versatile engineering verification solution for IC design houses.
In addition, the TR6836 features 8-site parallel testing capability, TTL or GPIB interface connection with prober and handler, a robust operation interface, and powerful statistics functions, which makes it an efficient yet powerful production testing solution for IC testing service provider companies.

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4/8M/16M pattern memory, 4K fail memory |
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Complete functional pattern and DC parameter testing |
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Timing generator, level set, current load, and I/O per pin configurable |
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16 on-the-fly time sets |
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8 independent V/I Resource |
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4 Device power Supply per Board |
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Shmoo Plot feature for engineering analysis |
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Superb test program debugging tools, and logic waveform display |
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Complete testing statistic reports and histogram |
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TTL or GPIB interface connection with Prober and Handler |
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8 sites parallel testing for mass production |
4M/8M/16M Vector Memory
The tester applies a sequence of drive data to the device and simultaneously compares the outputs against expected results. Each drive/compare cycle is called a digital vector. The TR6836 supports 4M (mega-), 8M or 16M vectors per test pin, depending on configuration. This provides comprehensive testing with the most flexibility.
8 Site Parallel Testing for Mass Production and Test Houses
TRI's IC testers feature muti-site testing. This means that the TR6836 can test eight dies on a wafer simultaneously, not just one. This greatly increases test throughput and helps reduce our customers' overall testing costs.
Wafer Testing Gives Early Feedback, Saves $$$
The earlier a defect is found, the cheaper it is to fix. Defects in finished goods can be very costly in terms of warranty and replacement costs. Probing wafers eliminates bad devices before packaging and final test, gives immediate yield information and analysis at the wafer level, and helps to monitor yield and quality for high-yield products.